资源列表
i2c_master_slave_latest.tar
- i2c master slave VHDL code
usb11_sim_model_latest.tar
- VHDL/Verilog implementation
ethernet_tri_mode_latest.tar
- TRI Ethernet implementation in VHDL
LCD126484显示汉字
- FPGA项目设计，12864显示汉字。。。。。。。(FPGA project design, 12864 shows Chinese characters.)
数字钟(8)
- 数字钟（总）整点报时，8位数码管显示。VHDL语言设计。。。。(Digital clock (total) the whole point timekeeping, 8 digital display. VHDL language design....)
Nexys4FFTDemo-master
- A simple Verilog example of a 4096pt FFT on analog input from a Nexys 4 XADC. The input is sampled at 1MSPS, oversampled to produce 14-bit samples at 62.5kHz, then sent to the FFT processing modules and passed through to PWM Audio out. The FFT output
12864c程序
- 本程序设计属于自己学习12864液晶屏的一些心得，里面程序循序渐进，从学习到集成的进步，适合初学者使用(This design program belongs to some of your learning 12864 LCD screen and inside program step by step, from learning to the progress of integration, suitable for beginners to use)
STM32开发简易直流电机速度环PID闭环控制
- STM32控制多路直流电机、PID速度闭环控制(STM32 control of multi speed DC motor and PID speed closed loop control)
STM32启动文件
- stm32启动文件(stm32)
04_uart_test
- 串行通信程序，Verilog示例程序，通用RS232(Serial communication program)
新建 Microsoft Word 文档
- CAN 接收器总共有 5 级接收 FIFO，在接收过程中，收到的报文将会依次在 5 级的输入 FIFO 中进行保存。CAN 中，5 个报文缓冲器在工作过程中通过转换被 交替映射到单片机的每个存储器区域内。RxBG（后台接收缓冲器）只与 MSCAN 相联系，前景接收缓冲器能够通过 CPU 寻址。(The CAN receiver has a total of 5 stages to receive the FIFO, and in the reception process, th
myProject2
- LAUNCHXL-F28027 开发例程(led,key,pwm,sci,epprom Development routine it is good for studying dsp28027)