资源列表
firnew
- 数字滤波的设计:FIR滤波器,设计滤波器采样频率为600hz,截止频率200hz的高通滤波器-Digital Filter Design : FIR filter, the sampling frequency filter design to 600hz, 200hz cutoff frequency of the high pass filter
VxWorkBSP
- VxWorks操作系统指南 VxWork BSP VxWork BSP-Guide RTOS VxWorks BSP RTOS BSP
CLKCP01
- 液晶显示器320*240脉冲实现,每出现12个clk出一个字节脉冲,每出现40个字节脉冲出一个行脉冲。240行结束出一个帧脉冲.-LCD 320 * 240 pulse realized there every 12 clk byte out a pulse, with each 40-byte burst out a pulse line. 240 firms from the end of a frame pulse.
7_4859_1
- 卡内基梅陇大学verilog课程讲义,希望大家能够喜欢!-Verilog University of Paisley and Adams Carnegie Course Training Manual, we hope to love!
44vhdl
- 44个vhdl实例 注1: 含有不可综合语句,请自行修改 注2: 一些PLD只允许I/O口对外三态,不支持内部三态,使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件,并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I / O exte
T80_v300
- t80 vhdl source code -t80 VHDL source code
lzo-1.08-src
- lzo-1.08-src.zip 高效的压缩解压代码-LZO - 1.08-src.zip efficient compression decompression code
unicntr
- 通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic -part of the general purpose registers IEEE code LIBRARY USE traffic IEEE.STD_LOGIC_1164
labplc
- pic 单片机 的简易PLC labplc.zip-pic microcontroller simple PLC labplc.zip
hiervhdl
- Using Hierarchy in VHDL Design vhdl语言初学者的天堂-Using VHDL Design VHDL language beginners paradise
T65_v301
- 微处理器核源码 like 6050 单片机-source like nuclear microprocessor 6050 MCU
picpas_src
- PIC 单片机 PAS SOURCE CODE SAMPLES-PIC PAS SAMPLES SOURCE CODE
