资源列表
The_Softening_of_Hardware
- The software and hardware development fields evolved along separate paths through the end of the 20th century. We seem to have come full circle, however. The previously rigid hardware on which our programs run is softening in many ways. Embedded syst
CANOpeniodesign
- CAN总线控制器的初始化程序，以及其它通信功能的分析和应用-CAN bus controller initialization procedures, as well as other communication and application of functional analysis
ARM7_stepmotor
- ARM7驱动步进电机的程序 -ARM7_stepmotor.txt
howtodoCANopendevelop
- 1. 先看看协议介绍，周立功网站上有些；对CANopen有个大致了解，分析一下是否适合自己的方案应用。 2.去cia下载301协议看看 3.下载个简单的协议栈代码(论坛上有),结合协议文件仔细分析，并把它移植到你的DSP上。 4.根据功能要求编写和完善自己的协议栈。 -1. Take a look at the agreement, the site some weeks Ligong of CANopen has a broad understanding and analy
Keil
- hx8347 初始化,刷屏,图片显示，图片下载，FLASH读写，液晶屏显示-hx8347 initialized刷屏, picture show, picture download, FLASH reader, LCD screen display
Single-chip_interface_technology_SRC
- 《单片机接口技术实用子程序》配套源代码,内有串口通信,并口通信等,共8章-" Single-chip interface technology utility subroutine" complementary source code
FPGA_overview
- code for fpga is written in verilog,cardinality is a thing which is very important
bcd99
- 设计了一个计数范围是0到99的BCD计数器并可以显示出来的-Designed a range of counts 0-99, and the BCD counters can be displayed
Adder4
- 本设计是设计了一个4位全加器的内容，是由4个一位全加器串联而成的-The design is to design a full adder 4 content, is one of four full adder in series from the
Verilog_example_guide
- 详尽介绍了VERILOG编程过程中的组合逻辑和时序逻辑设计方法，同时对仿真程序的编程和使用也做了完美的讲解，便于快速学习掌握-Detailed descr iptions of the course of the VERILOG a combination of programming logic and sequential logic design, simulation program at the same time the use of programming and have als
sevenvote
- 本设计师一个7人表决器，用7个开关作为7个输入变量，输入变量是 1 时表示赞同，输入变量为 0 时表示不赞同。-The designer of a voting machine 7 with 7 switch 7 as input variables, input variables is a' 1 ' when agreed input variables for the' 0' that do not agree with.