资源列表
ppx16
- ppx16系列单片机的vhdl内核代码，并根据该内核实现了P16C55和P16F84两款单片机。-Vhdl code of ppx16 series MCU core, and includes the realization of two MCU- P16C55 and P16F84 according to this core
fm
- DOS下的基于研华PCL836的采集卡的c测评程序-frequency measure C source code under DOS system based on PCL836 card
main_dct
- verilog code for dct
FPGA_design_of_a_pipelined_CPU
- 基于FPGA流水线CPU控制器的设计与实现：在FPGA上设计并实现了一种具有MIPS风格的CPU硬布线控制器。-FPGA design of a pipelined CPU：a hard-wiring CPU controller with a MIPS-style is designed in FPGA.
i80386
- Intel微处理器80386的vhdl模拟，很有参考价值-Vhdl simulation of intel s 80386 microprocessor, is valuable for reference
fft_fpga
- 自己写的一个关于fpga开发的fft模块。-Wrote it myself on the development of fpga module fft.
FileOperate
- wince 文件操作例子,wince file operation-wince file operation,wince file operation
vaa
- （１）设计一个4位十进制的频率计其测量范围1Hz~9.999KHz；6 N3 G8 k( U- @ n* A （２）记数过程结束后，保存并显示结果；-(1) to design a metric four of its frequency range 1Hz ~ 9.999KHz 6 N3 G8 k (U-@ ' n* A (2) After the counting process, preserve and display the results
uart_my
- 自己设计的串口verilog代码，已在fpga上跑过，问题无误。-Serial verilog design code, ran in the fpga, correct the problem.
Realization_of_8051_microcontroller_core_based_on_
- 基于流水线架构8051微控制器内核的实现，上海交大的一篇硕士毕业论文，很有参考价值-Realization of 8051 microcontroller core based on pipelined architecture, a master s thesis of Shanghai Jiaotong University, is valuable for reference
router_fifo
- 自己写的一个片上网络路由节点的fifo模块，工作频率达到1ghz。-Himself wrote a piece on the network routing node of the fifo module, the work frequency of 1ghz.
pwm__vhdl
- 一个基于vhdl语言的脉冲宽度调制。并且有两个脉冲输出-Vhdl language-based pulse width modulation. And two pulse output