资源列表
usb_xilinx_vhdl
- FPGA核心部分源码，了解FPGA运行原理-FPGA core of the source code to understand the operating principle FPGA
music
- 用VHDL 语言设计实现一个10 秒倒计时电路，要求使用8×8 点阵显示计时结果。能在计时到0后开始播放乐曲，同时乐曲可以自由转换。-VHDL Language Design and Implementation with a 10 seconds countdown circuits require the use of 8 × 8 dot matrix display time results. To 0 in time to start playing after the music, a
usbip
- USB接口控制器参考设计，xilinx提供VHDL代码 -USB interface controller reference design, xilinx provide VHDL code
FPGAcoreofthesource
- FPGA核心部分源码,了解FPGA运行原理-FPGA core of the source code to understand the operating principle FPGA
S3C6400_Routing_Guide_Rev0.0_20070205.pdf.tar
- Samsung S3C6400_Routing Guide_Rev0.0_20070205.pdf
design
- The verilog implementation of 8-point FFT in verilog. Radix 2 Decimation in Frequency.
__sdram
- Using SDRAM MT48LC4M32B2-7 in the LPC2468
numerical_methods_-_real-time_and_embedded_system
- Numerical Methods - Real-Time and Embedded Systems Programming-Numerical Methods- Real-Time and Embedded Systems Programming
WASv7_FineGrainedLab
- the steps to configure fine grained security on websphere 7.0 console
Fir
- 基于TMS320F2812的FIR数字滤波器-FIR filter for F2812
SPI
- 基于TMS320F2812的SPI串口外围设备源码-SPI for TMS320F2812