资源列表
plc
- QSPLC系列可编程控制器实验 数码显示的模拟控制 交通灯的模拟控制（控制过程、I/O分配、控制语句表、梯形图）-QSPLC series programmable controller experimental digital display analog analog control traffic light control (control process, I/O distribution, control statement table, ladder)
bcd
- 4位bcd码加法器的verilog代码 -4 bit bcdadder verilog4 bit bcdadder verilog
DSB3
- 利用ISE软件编写的Verilog程序，可以进行信号的双边带调制-Using ISE software program written in Verilog, can be bilateral with a modulation signal
cordic
- altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
xiangweileijiaqi
- 相位累加器，是数字频率合成器的重要组成部分。这是verilog代码。-Phase accumulator, digital frequency synthesizer is an important part. This is the verilog code.
I2C
- I2C总线接口的Verilog源码文件和modelsimd的测试文件-Verilog source code of I2C bus interface and testbench code of modelsim.
hdb3_codedecode
- 用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功-Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation
askcodec
- verilog实现ask编码器，仿真通过-ask encoder verilog implementation, simulation by
uart_read_send
- uart自收发的vhdl实现,包括quartus工程文件及modelsim仿真工程文件(调试通过)-uart vhdl from the transceiver to achieve, including the quartus project file and modelsim simulation project file (debugged)
Sdram_Control_2Port
- 双端口SDRAM控制器，将SDRAM虚拟成两个端口，已经在ALTER DE2开发板的硬件上验证通过，采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language.
design_checklist
- the checklist of FPGA design
fifo2
- 异步双时钟fifo，vhdl源代码。基本组成是定制的fifo加上空满判断逻辑，基本功能都有-Asynchronous dual clock fifo, vhdl source code. Fifo basic component is a custom air filled with the logic to judge the basic functions are