资源列表
Manchester_QuartusII
- 完整的曼彻斯特编解码(采用锁相环技术）_QuartusII工程-A complete QuartusII project for Manchester coding and decoding with phase-locked loop technology
Jpeg_decoder
- It is jpeg_decoder program. Source code are C and Verilog HDL.File .c reads data from jpeg and convert it to binary bit stream.Decoder is by verilog file
mean
- 3x3 Average filter in VHDL
Locking_device
- EDA课程设计，基于DE2板的八位十进制锁码器，vhdl源程序！-EDA curriculum design, based on the DE2 board to eight decimal lock code reader, vhdl source code!
clock_timer
- 数字电子钟实现了真实的时间计数，通过这个工程的训练，能更好的了解Quartus II数字电路开发的过程。--Digital electronic clock to achieve a real time count, the training through this project, to better understand the Quartus II development process of digital circuits.-
robot_control_library_latest.tar
- 机器人相关资料，采用vhdl语言编程设计，来源opencore,许多例子-Robot-related information, using vhdl programming language design, source opencore, many examples
SDRAMPNIOS-II
- 带SDRAM的nios II系统，开发环境为Quartus II 9.0 + Nios II 9.0-With the nios II SDRAM system, development environment for the Quartus II 9.0+ Nios II 9.0
memc_with_fifo
- Verilog编写的Memory Controller代码，用于AMBA总线下-Verilog code written in Memory Controller
UART_DMA
- 基于DE1的nios的串口sdram通信例程-Based on DE1' s nios serial communication routines sdram
BCDadd8
- 8位的BCD加法器，BCD表示即4bit表示一个十进制数，取值范围是0000-0110，verilog代码实现-8-bit BCD adder, BCD said that 4bit represents a decimal number, range is 0000-0110, verilog code
MSequenceGenerator
- 5位的M序列发生器，verilog代码实现。5次本原多项式采用f(x)=x^5+x^2+1-5 of the M-sequence generator, verilog code. 5 using a primitive polynomial f (x) = x ^ 5+ x ^ 2+1
DSP-External-Memory-Interface-Module
- EMIF是DSP嵌入式系统中重要的外扩接口，往往连接大容量/高速存储器、并行AD/DA、外扩特殊功能芯片，甚至连接FPGA或者ASIC。-EMIF is a DSP embedded system is an important external expansion interface, often connect large-capacity/high-speed memory, parallel AD/DA, outside the extended special function chi