资源列表
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
FLASH_WR
- 本文件为用Verilog写的FLASH S29AL032D读和擦除的驱动时序，对刚学习Verilog的同学有一定帮助，已在DE2开发板上验证。-This document is written in Verilog FLASH S29AL032D read and erase the drive timing of the students just learning Verilog will definitely help, has verified the DE2 board.
pid_controler_latest.tar
- PID控制器的verilog实现，做闭环控制器的人可以参考-PID controller verilog implementation of closed-loop controller may make reference to
solutions_manual
- 数字系统设计与VHDL（第二版）Charles H.Roth, Jr.Lizy Kurian John著 金明录 刘倩译-solutions manual to digital systems design using vhdl, second edition
endat_c
- 用于读取海德汉绝对位置编码器的位置数据。ENDAT2.1接口-Read the data from ENDAT2.1
dma_ahb_latest.tar
- this shows the ip code for dma controller of amba ahb in vhdl.
fsk
- FSK 完整 支持两板间 通信 位同步 帧同步-FSK full support for communication between the two plates synchronization frame synchronization
dwt2d_latest[1].tar
- 小波变换的开源代码（Verilog HDL）包括有测试文件，本人看过，挺好。-code of dwt
Omnivision SCCB interface verilog model
- Omnivision SCCB interface verilog model
LMS_filter
- verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
DM412_1ea_test
- 点晶DM412单颗级联测试程序，使DM412输出恒流，修改级联数可做点光源控制程序-DM412 single point crystal cascade testing procedures so that the output current DM412, modify the number of cascade control procedures can point light source
OV7620_TEST
- FPGA驱动OV7620程序代码，SCCB部分由单片机完成，FPGA负责完成图像处理和TFT液晶的显示。经试验，效果不错！-FPGA-driven OV7620 code, SCCB completed in part by the microcontroller, FPGA responsible for the completion of image processing and TFT LCD display. The test, good results!