资源列表
7segment
- a vhdl code for 7-segment
ALU
- a vhdl source code for ALU
BCD counter( state machine)
- a vhdl source code for BCD
comparator
- a vhdl code for comparator
DFF
- a vhdl source code for dff
timer_24
- 实现数字钟功能，带有按键调整时间，定时闹钟功能(Digital clock function, with timing, alarm clock function)
FPGA开发实战手册 V1.1
- 介绍了fpga的开发流程，对实际案例进行源码剖析，清楚易学(Introduced the FPGA development process, carries on the source code analysis to the actual case, clear is easy to learn)
yuanma
- 介绍了fpga开发的的数个工程源码，包括按键，时钟，AD/DA，VGA，数字示波器等(Introduced FPGA development of several engineering source code, including buttons, clock, AD/DA, VGA, digital oscilloscope, etc.)
sd_gen
- 标清信号fvh，75%彩条，包括pal50hz和ntsc60hz(sd generation 75%bar fvh)
PPM采集和综合测试程序
- PPM信号的采集以及 综合测试程序.zip(PPM acquisition and integration test program.Zip)
CMA
- 用Verilog实现FSE-CMA算法，分为四个模块，一共迭代8次(Implementation of FSE-CMA algorithm with Verilog)
AD7606_1
- ad7606采集Verilog 编写的模块 有仿真图(ad7606 Verilog ad7606 Verilog)