资源列表
project1
- fpga应用开发简单的小工程，供初学者学习-fpga simple little application development projects, for beginners to learn
project2
- 关于verilog有限状态机的设计，可以供初学者对有限状态机的设计有初步了解-About verilog finite state machine design, finite state machine for beginners to have a preliminary understanding of the design
lcd12864
- 实现对LCD12864的中英文调试，已经验证通过-the LCD12864 TEST IS OK
guangshanchi
- 实现光栅的四分频以及相位的判断和脉冲的计数，实验调试通过-THE TEST IS OK
verilogiic1121
- fpga通过i2和e2prom通信，调试通过，可以直接拿来用-the test is ok
UART_16750_vhdl
- UART串口FPGA源文件，VHDL设计文件，兼容16750-UART FPGA VHDL 16750
jpb_ise12migration
- 旋转编码 功能性键盘编码 spi时序发送数据-cycle key code
music
- Music demo verilog file
VERILOG-Simulation
- This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus using netlabel. The Simulation c
16Bit-Group-Ripple-Adder
- Verilog Testbench for 16Bit Group Ripple Adder
BCD-Counter
- Verilog Module for parity
Error-Correcting-For-7bit-Hamming-Code
- Verilog Module for a 3 to 8 bit decoder