资源列表
lisa-vhdl2va
- 通过modelsim仿真检测matlab生成滤波器效果。-Generate the filter through matlab and simulated by modelsim.
8051_test
- 在FPGA上，可用的8051核。用Quartus II 9.0调试通过。-On the FPGA, available 8051. With Quartus II 9.0 debugging.
chuankouex
- 基于FPGA的串口通信的电路设计，以RS-232c作为设计标准-serial communication
VGAsignal
- Verilog 典型的VGA 显示 有按键控制的不同彩色的图像-Verilog VGA display
prog_seq_FIN
- Verilog Programmable Sequence Detector on Spartan3E
Counter_Debounce
- Verilog 3-bit Inc/Dec Counter on Spartan3E
paobiao
- ISE仿真平台下建立的用verilog语言实现的简易数字跑表工程-Simple digital stopwatch works with verilog language of the establishment of the ISE simulation platform
VGA-a353
- PROGRAM FILE ...... XILINX ISE DESIGN....2014
beep
- 学习FPGA的入门程序，采用verilog语言，对时钟进行分频，控制蜂鸣器发声，可以发出七个音色，希望大家好好学习学习。-Learning FPGA entry procedures, using verilog language, clock frequency, control the buzzer sound can be issued seven tones, I hope you learn to learn.
src
- 波形发生器，可产生方波，正弦波，三角波，锯齿波，幅度可调，频率可调-Waveform generator can produce a square wave, sine wave, triangle wave, sawtooth wave, amplitude adjustable, adjustable frequency
gcd_power
- 用硬件描述语言实现求最大公约数，使用FSM-using hdl implements the gcd with gsm
method1
- 脉动乘法器的HDL实现，包括DC、Astro跑版图-using HDL implements GM multiplier，including src，DC，and Adtro layout