资源列表
ReactionTimer
- Reaction Timer verilog code, can be downloaded on texas NEXYS2 or NEXYS3 board to test the reaction time by pressing the buttons.
FIFO
- This a simple example of FIFO(first in and first out) module written in verilog code-This is a simple example of FIFO (first in and first out) module written in verilog code
PNgenerator
- This is a simple example of PNgenerator which use the clock signal inside the NEXYS3 board.This is basically a 8-bit PN number added by 256. The initial value cannot be all zeroes.
Binary_to_BCD_Converter
- This is a binary to BCD convert designed by using the “shift and add-3 algorithm”. The verilog code of basic cell add-3 is also included in this file.
StopWatch
- This a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.-This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
Counter
- Counter in VHDL using Xilinx ISE
seg7_driver
- verilog七段数码管驱动，显示内容可以自己更改。-verilog segment digital tube driver
Basys2UserTest
- 由digilent生产的basys2开发板用户测试程序VHDL版-Produced by the digilent basys2 development board user testing procedures VHDL version
ADS8325
- ADS8253，8位串行高速AD转换芯片的FPGA驱动程序，verilog语言版本-ADS8253, 8-bit serial high-speed AD converter chip FPGA driver, verilog language version
gen_divd
- FPGA分频器，verilog语言版本，通过实例化参数实现任意整数倍分频-FPGA divider, verilog language version, by instantiating an arbitrary integer multiple parameters Divide
ZRtech-CORE
- 淘宝卖家ZRTECH核心板的程序与PDF说明-ZRTECH core board procedures and instructions PDF
1602test
- Verilog AD转换1602显示，用QuartusII编写的。完整的工程，好使！-Verilog AD converter 1602, with QuartusII prepared. Complete works, so that!