资源列表
BCD-counter
- 一个2位的BCD码十进制加法计数器电路，输入为时钟信号CLK，进位 输入信号CIN，每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT，输入时钟信号CLK用固定时钟，进位输入信号CIN. -A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output s
ulpiereport.tar
- 开源的ULPI IP核，可用于USB3300芯片的开发-openSource ULPI IP core which could be used for USB3300 chip development
LMS
- 用verilog编写的lms算法。可实现自适应滤波功能-Lms algorithm written in verilog. Adaptive filtering can be achieved
verilog-master-files
- Verilog master files of AMBA axi interface
STFT
- 短时傅里叶变换的FPGA实现零重复度使用了fft的IP核设计-When the Fourier transform of the FPGA to achieve zero repeatability using fft IP core design
jtag
- verilog语言编写的jtag（边界扫描模块），初学的时候可以-verilog language jtag (boundary scan module), a novice when you can look
uvm_use_pipelined_ahb
- 一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本-one sample example about ahb，include every component and compile scr ipt
CLZ32
- 针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。-The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The n
Crack_QII_13.1_Windows
- 采用骏龙科技这个13.1新版本破解器.对于已经用了老版本破解器的网友，请把bin和bin64下的sys_cpt.dll删除，然后把sys_cpt.dll.bak名字改成sys_cpt.dll，也就是先恢复正版，然后用这个破解器破解。注意老的license文件也要删除，改用这个新版本破解器附带的license-Cytech Technology 13.1 using the new version of this cracker. Has been used for the old version
AD7606URAT
- Verilog实现高速AD7606数据采样，8通道，采样频率可调，支持串口数据发送，亲测可用。-Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
TSE_RGMII_With_SDC
- Altera 官方tse三速以太网IP核RGMII使用例程-Official Altera Triple-Speed Ethernet IP Core RGMII using routines