资源列表
Decoder
- This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder
bus
- 一个简单的总线bus代码，初学者可以借鉴学习-A simple bus-bus code, beginners can learn to learn
shiftreg
- 本代码实现了移位寄存器功能，初学者可借鉴学习-This code implements the shift register functions, beginners can learn to learn
486bus
- 本代码实现了486总线的功能，初学者可以借鉴学习-This code implements the 486 bus functions, beginners can learn to learn
outshiftreg
- 本代码实现了输出移位寄存器功能，初学者可以借鉴学习-This code implements the output shift register functions, beginners can learn to learn
hello_led
- 在FPGA开发板显示字符串,采用VHDL语言,以简单的功能说明FPGA的开发流程.-In the FPGA development board shows the string, using VHDL language, in a simple functional descr iption FPGA-development process.
fulladder
- 本代码实现了全加器的功能，可供初学者学习-This code implements a full adder functions, for beginners to learn
shuzizhong
- 这时用VHDL语言编写的多功能数字钟，具有正常的计时功能，还能进行校时、校分，并且具有整点报时功能-Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of
audio_codec
- i2s协议时飞利浦公司专门为开发音频而开发的协议，这是它的VHDL代码，希望有帮助-i2s agreement, Philips developed specifically for the development of the audio protocol, which is its VHDL code, and want to help
mc8051
- Oregano Systems 8051 ip核-Oregano Systems 8051 ip core
shuizhongvhdl
- 这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
jiaotongdengsheji
- 这是一个交通灯控制的VHDL程序，用于maxplus平台，适合于EDA设计-This is a traffic light control, VHDL program for maxplus platform, suitable for EDA Design