资源列表
Xilinx_yuanyu
- 本文详细介绍了xinlinx公司fpga的原语使用方法，原语相对于调用核来说更简单明了，推荐初学者多使用原语-This paper describes the xinlinx' s fpga use the original language, the original language as opposed to call-core is more simple and straightforward, it is recommended for beginners to use mor
dds_key_bak
- DDS控制部分 数码管显示，可选择多种波形，频率可控-DDS control part of digital tube display, choose a variety of waveforms, frequency controlled
flash_rom
- flash_rom 将拥护数据存储在flash_rom中，然后读取flash_rom里面的数据-write and read flash_rom
SDRAM_controler_code
- SDRAM的verilog控制器代码极其仿真模块-The verilog code for SDRAM controller is extremely Simulation Module
vhdlLCD1602
- 用CPLD控制1602显示汉字，内含三个模块-1602 with the CPLD control display Chinese characters, contains three modules
Arbiter
- Arbiter unit includes client and server units. Used for Arbitation of multipliers in Altera FPGA based project. The code supports several multipliers and several clients with different priorities.-Arbiter unit includes client and server units.
4lundingwei
- 汽车4轮定位系统的源代码，在阿特拉MAX8000系列上用MaxplusII调试通过（7000系列不能用），直接烧入cpld即可。-4-wheel vehicle positioning system source code, in the atrazine MAX8000 series on debugging with MaxplusII adopted (the 7000 series can not be used), can be directly burned into the cpl
VerilogHDL
- Verilog HDL 程序设计实例详解 Verilog HDL 程序设计实例详解-Verilog HDL programming example explanation example explanation of Verilog HDL programming
DDSFunctionGenerator
- 能实现频率步进100hz的信号发生器，频率可调。100-20khz.-To achieve step-100hz frequency signal generator, frequency adjustable. 100-20khz.
ad80518253
- fft 单片机+fpga+8051core-fft MCU+ fpga+8051 core
dds
- VHDL编的CPLD正弦波产生程序用直接数值合成DDS原理驱动dac0832实现正弦波输-VHDL compiled CPLD sine wave generation process by direct numerical synthesis of theory-driven dac0832 achieved DDS sine wave input
vhdlprogrammes
- vhdl programmes of state machine