资源列表
uartvhdl
- 用VHDL语言实现UART的通信协议，可以实现与其他外围设备的通信。-it use vhdl realize the uart，it can help you communicate the to communicate。
VHDL100
- 这是一个包含100例精典VHDL语言例子的压缩包,里面有详细的程序说明.-This is a VHDL language that contains examples of 100 cases of classics compressed packets, which have a detailed descr iption of the procedures.
TheFPGALadyBugProject
- This document is about project that use FPGA
InterefacingPS2Keyboard
- FPGA/keyboard interface is shown in figure 1. When the FPGA “reads” the Data or Clock inputs both PS2Data_out and PS2Clk_out are kept low which puts the tri-state buffers in high impedance mode. When the FPGA "writes" a logic 0 on an output, the
myself3
- FPGA 接一个高速AD。。在模拟示波器上实现逻辑分析仪的功能-FPGA logic
HDL
- 这是一个高手写的关于如何提高HDL的编程能力，很有好处的。-This is a master to write about how to improve the capacity of HDL programming, it is beneficial.
i2c
- This code implements the control of the i2c bus with a MC68000 type interface. It is modeled from the M-bus component in certain Motorola uC. The I2C control is done in the component i2c_control and the uC interface is implemented in the component u
quartusii_handbook
- 关于quartus最权威和最详尽的说明和指导，是一个很好的新手入门的handbook-About quartus the most authoritative and detailed instructions and guidance, is a good novice' s handbook entry
mc8051_MYdemo
- 51IP核一些资料， 很好可以根据自己的需要进行定制，方便自己设计。-51IP Nuclear some information, well you can customize according to their own needs to facilitate own design.
Lock
- 密码锁，本设计是根据小区的门，来设计的。这个设计，可以减少一个保安，什么的。具有使用价值。-Lock, the design is based on cell doors, to design. This design can reduce a security, or something. Has a value.
vhdl_jk
- 本程序通过使用vhdl语言描述JK触发器，实现了JK触发器的四个工作状态，进而我们可以将其应用到其他使用JK触发器的电路中-The procedure by using vhdl language to describe the JK flip-flop, JK flip-flop realized the four working state, then we can apply it to others using the JK flip-flop circuit
add
- 实现加法、减法及循环累加运算，同时有溢出判断的verilog程序，已经验证-To achieve addition, subtraction and recycling accumulation operations, while there is overflow judge verilog program has been verified