资源列表
compare
- 基于FPGA的VHDL设计。可以比较任何类型数据的大小关系。-The VHDL-based FPGA design. Can compare the size of any relationship between the type of data.
p15_gen4
- VHDL module for parallel (4bits) PRBS 2E15-1 generation
8085
- 8085 vhdl source code in vhdl
picoblaze_interrupt_controller_latest.tar
- picoblaze microcontroller
FPGA
- 讲解FPGA软件的开发流程和设计注意事项-the ppt for designing FPGA
cpld
- 基于CPLD的总线控制逻辑，完全正确经调试-CPLD-based control logic of the bus, completely correct by the debug
etester_zcx1002
- 这是一个等精度频率计的VHDL源程序，里面有QuartusII的完整工程文件。-This is a precision frequency meter, such as the VHDL source code, which has a complete project file QuartusII.
Muliterfovhdl
- 基于vhdl硬件描述语言的快速乘法器设计-Muilter for vhdl
dds_9760_OK
- ＤＤＳ信号源程序，用ＶＨＤＬ编的。里面可用拨码开关选择相应的功能：ＦＭ，ＡＳＫ，ＰＳＫ，ＡＭ（这一点实现的不是很好），但其它的很好。频率可达２５Ｍ-DDS signal source, for the use of VHDL. DIP switch which can be used to select the appropriate function: FM, ASK, PSK, AM (This is not to achieve good), but other well. Frequen
SystemC-Tutorial
- systemc 教程,硬件描述语言，交易级建模，语法-systemc tutorial for ground up
vhdl_slides
- vhdl课件，缪善林，哈尔滨工程大学信息与通信工程学院-vhdl
my_uart_top
- 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and recei