资源列表
quartus-train
- 这是一款CPLD的在线调试软件。能够满足用于学习者的一般要求。-This is a debugging software online CPLD. Be able to meet the general requirements for learners.
ADC0809VHDL
- 文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Descr ipt
Quartus7.2andModelSim
- 结合截图，quartus2与ModelSim的联调的详细操作步凑，使初学者迅速上手-Combination of shots, quartus2 with the ModelSim FBI put together a detailed step-by-step operation, so that beginners get started quickly
i2c
- i2c硬件程序,字节读、字节写，在modelsim6.0通过编译-the soft for i2c
farsight081129FPGA
- 高性能FPGA应用领域及其研究，FPGA的开发流程-High-performance FPGA applications and research, FPGA development flow
top_pnadd32
- 32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
cpu
- 32位元浮点CPU,用VHDL语言以类似组合语言的方式写成-32 floating-point CPU(VHDL)
cpu
- 16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
x95288x
- VHDL的寄存器读写参考，可自己根据要求重新修改，本示范只做参考用-Register read and write VHDL reference to their request to amend in accordance with, the reference model only
fifo_bde
- FIFo参考设计16x32 FIFO with simultaneous read/write operations.-FIFO design-16x32 FIFO with simultaneous read/write operations.
Generator
- This a simple pulse generator. It generates a pulse-This is a simple pulse generator. It generates a pulse
memory_example
- This simple example allows you to get familiar with Active-HDL s Memory Viewer.