资源列表
logic
- 5位的操作数X和Y输入后暂存在寄存器A和B中，两位的操作控制码control暂存在寄存器C中，按照control码的不同，分布实现下列操作： 00控制X+Y 01控制X-Y 10控制X and Y 11控制 X xor Y 运算结果暂存在寄存器D中，然后输出。 -5 of the operand X and Y after the temporary importation of A and B in the register, the two operational c
AlteraFPGACPLD1
- Altera FPGA_CPLD设计 基础篇-Altera FPGA_CPLD Part Design
32bit_RISC_CPU
- 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
ddr_dimm
- 256Mb_ddr 实现ddr_dimm操作-256Mb_ddr achieve ddr_dimm operation
logicassign
- 同一基类型的两分辨类型的赋值相容问题,各个源描述的编译顺序是:logic.vhd,assign.vhd-The same base type to distinguish the two types of assignment compatibility issues, the various sources described in the order of the compiler: logic.vhd, assign.vhd
GCD
- 最大公约数的计算,各个源描述的编译顺序:gcd.vhd,gcd_stim.vhd-The common denominator of the calculation, the various sources described in the order of the compiler: gcd.vhd, gcd_stim.vhd
gcd_disp
- 最大公约数七段显示器编码,各个源描述的编译顺序gcd_disp.vhd,vhdl.vhd,stim.vhd-Seven-Segment Display common denominator coding, various sources described in order to compile gcd_disp.vhd, vhdl.vhd, stim.vhd
TLC
- 交通灯控制器编码，源描述的编译顺序tlc.vhd，est_vector.vhd-Traffic lights controller code, the source described in order to compile tlc.vhd, est_vector.vhd
conditioner
- 空调系统有限状态自动机编码，各个源描述的编译顺序conditioner.vhd，conditioner_stim.vhd-Air-conditioning systems finite state automata encoding, various sources described in order to compile conditioner.vhd, conditioner_stim.vhd
fifos
- 通用的ｆｉｆｏ设计，带有ｔｅｓｔｂｅｎｃｈ，和ｄｅｓｉｇｎ＿ｆｌｏｗ-Fifo generic design, with a testbench, and design_flow
qingdaqi
- 四路抢答器，超时报警，提前抢答报警，计分等-Answer four, and overtime alarm, warning in advance Answer, including classification