资源列表
masser_AC97
- ac97 VHDL core
USB 1.1 IP-CORE和设计范例 VHDL源代码
- USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
shuzi1216
- vhdl 语言入门-VHDL language portal
基于半加器的全加器描述及仿真
- vhdl基于半加器的全加器描述及仿真-VHDL-based increases for the entire increase Descr iption and Simulation
pwm
- 基于vhdl的PWM发生器-VHDL-based PWM generator
026030065王银涛VHDL
- 7段数码显示译码器-seven of the digital display decoder
VHDL作业－张晓峰036099149
- VHDL的四选一选择器-VHDL four elected a selector
3-8译码器
- vhdl的3-8译码器-instantiate the 3-8 decoder
VHDL大作业－虞益挺036100486
- 全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
付铁刚036089095
- vhdl寄存/计数器设计-VHDL Storage / counter design
vhdlxdh
- 带同步复位信号的二分频VHDL 程序-synchronous reset signal with the two-frequency VHDL procedures
朱明辉vhdl大作业
- 一个双向总线的vhdl实现-a two-way bus VHDL achieve