资源列表
EDAchuzuchejijia
- 在本示例程序中，用VHDL语言实现了出租车的记价功能，在Maxplus2环境下编写，可通过cpld下载板来验证程序。在压缩包中附有示例的目的，方法和仿真时序图，是学习VHDL好例子。-in this sample program, using VHDL of the entry price of a taxi function, in preparation FLEX10K environment, through cpld download plate to the verification
cpldcontrol
- 一段cpld的控制程序，可以进行传并转换，读写接口，每秒64k-a cpld control procedures can be done - and switching to read and write interface per second 64k
addsub_core_
- hdl的8051核，不知道好不好用大家试试吧。xilinx公司的核-HDL 8051 nuclear, we know that is really useful to try it. Xilinx's nuclear
addsub_cy_
- 加法器核，带进位位的，xilinx公司的核，能用-Adder nuclear, into place at the company's nuclear Xilinx can use
youxiufft
- 16点的fft程序.非常不错,编译已经实现,还是很好的-16:00 fft the procedure. Very good, compilers have achieved, or good
8051VHDL
- 一个C8051 内核的VHDL程序源代码-C8051 core of a VHDL source code
pluse_delay
- 利用VHDL语言实现单稳触发电路，稳态时间为系统时钟的整数倍。-using VHDL-trigger circuit stability, steady time for the whole system clock several times.
vhdlprogram
- 用复杂可编程逻辑器件(CPLD)实现的数字钟控系统-with complex programmable logic devices (CPLD) with a digital clock control system
TI6713DSKVHDL
- TI6713浮点DSP的DSK的VHDL。比较全面。可以编译运行。-TI6713 floating-point DSP DSK VHDL. More comprehensive. Compiler can run.
n_dc_motor
- vhdl实现的直流电机控制器 通用程序 对不同fpga/cpld，可能需要修改部分源代码。-VHDL achieved DC Motor Controller General of different procedures they simply / cpld. may need to amend some source code.
source_verilog
- verilog shi 实现的加法器（8位）适用于初学asic -Verilog realized Adder (8) applies to beginners blends
sdramcore
- sdram控制的内核，高手编的，已经调试过了，没有错误-SDRAM control of the kernel, the top series, has been tuned, no errors