- dirtre 使用VC++6.0开发的windows界面－树形目录
- MRI medical image loader and some simple opengl operation.
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- genetic-code 基于遗传算法写的关于旅行商问题的代码
- DCT_Denosing DTC去噪算法 matlab程序 简单适合初学者(DTC denoiseing processing which suits the students for studying)
- ctrllab3.0 Linear Feedback Control (Xue 2022)
资源列表
SHUMAGUAN
- avr单片机 atmega16 数码管循环显示数字0到9-avr microcontroller atmega16 digital control loop display numbers 0 to 9
Rolling_Message_Modified
- PicBasic program for PIC16F876A for LCD display. Rolling message displaying for attractive look.
sn7448
- verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."
fifo.v
- This the source code for FIFO -This is the source code for FIFO
subtractor
- Verilog source code for full subtractor module build with predefined nor gates.
NEC-AT24C256
- nec单片机完成对存储器AT24C256的读写-nec microcontroller to read and write AT24C256
main
- 利用改变定时器输出比较通道的捕获值，当输出通道捕获值产生中断时，在中断中将捕获值改变，这时，输出的I/O会产生一个电平翻转，利用这种办法，实现不同频率的PWM输出。-Used to change the timer output value of a channel down the output channel capture value generate the interrupt, "the value will change, then, the output of course i
divider
- Verilog语言编写分频器，用于数字竞赛式抢答器的设计模块之一-The Verilog language divider for digital contest Responder design module one
Decade-Counter
- decade counter with two input and count out outputs
sqrt
- 用verilog实现的开2次方，已经在modelism中经过验证，其时间周期不固定。-Implementation open square with verilog.
binbcd8
- Binary to BCD conversion in VHDL for implementation in FPGA
BCDto7Segment
- vhdl bcd to seven segment