资源列表
seqdet
- 串行序列检测器，以得到modelsim仿真波形，用verilog编写。-Serial sequence detector to get modelsim simulation waveform, prepared with verilog.
dm642_uart
- DM642串口中断程序，BIOS方式实现，所有非BIOS方式的程序都测试过，都没法进入中断，这种BIOS方式的可以进入中断-DM642 serial interrupt program BIOS achieved, all non-BIOS way procedures are tested, no law into interrupt this BIOS mode can enter the interrupt
5.3_Button_Test
- === === === === === === === === === === === === === === === = Button_Test实验 === === === === === === === === === === === === === === === = 本实验实现通过扩展IO来接收KEY1和KEY2的中断，并显示在超级终端上。本例程有两种运行方式。 Button_Test IN RAM 将程序下载到SDRAM中调试。 Button_Test IN
YL24X0-DEV-V20
- YL2440开发板扩展板原理图，结合核心板使用，基于S3c2440芯片
usb
- pic32MX795f512的USB 应用例子-pic32MX795f512 the USB application examples
AssignmentP7
- 1. Design a VHDL model for a 4-bit up-and-down synchronous binary counter with carry and borrow signs using FSM. Verification of this design is especially appreciated.
SDCard_fat16
- AVR单片机atmega169实现的SD卡的带文件系统FAT16的读写仿真，内有protues的仿真原理图，写入的数据可在电脑上读出，支持多层文件夹。-The AVR microcontroller atmega169 achieve SD card with a file system of FAT16 read and write simulation, within protues simulation schematic, the data can be written to be re
2
- 电子毕业设计集锦，600多个电子毕业设计题目-Electronic Graduation Collection, more than 600 e-Graduation topics
200804230018451
- 80x86汇编指令查询器(试用版)80x86汇编指令查询器(试用版)-80X86
tbcpu8bit2
- 极小的CPU的VHDL源代码，仅需要占用32个宏单元的CPLD。除了VHDL源代码还包括了汇编器的C源代码-minimal CPU VHDL source code, only occupy 32 macrocell CPLD. Apart from VHDL source code also includes a compilation of C source code
mult_8b_for
- 本实验使用Verilog语言 通过FOR循环完成8bit乘法器功能，通过ISE仿真测试，可实现综合-Verilog language used in this experiment through the FOR cycle completed 8bit multiplier function, through the ISE simulation tests can be integrated
CAN
- 基于s3c2440的 在ADS1.2环境下的确 CAN BUS驱动及测试程序