资源列表
cpld_bus
- CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
BIT1612_v023.RAR
- BITEK BIT161x slave mode C51 源代碼 BIT161x slave mode C51 源代碼, 可以支援 BIT161x 系列 (BIT1612/BIT1615 H/BIT1617/BIT1625). 1)支援 PLATFORM_05_DMO162501 (VID842-102-183/BIT162501) 2) 增加 BIT1625 DMO059000100. 3) 增加 BIT1625 DMO059000101.
SPWM
- 利用DSPTMS320F2812的事件管理器产生SPWM波形，应由于电力电子控制电路。-Use DSPTMS320F2812 event manager to generate SPWM waveform should be due to the power electronic control circuitry.
DS305LSSCN
- CANopen 305协议中文翻译，欢迎下载-CANopen 305 Chinese translation of the agreement are welcome to download
1
- 时钟是人们日常生活必不可少的一种产品，电子时钟因为其价格低廉、操作方便等优点深受消费者喜爱。本设计将以单片机为核心设计几种电子时钟的设计方案，这些方案中有的可以将其嵌入其他电子产品中，有的则适合单独作为时钟产品，有的时间准确，有的则时间粗略。能够满足不同场合、不同需要的情形。-Clock is essential for people' s daily life of a product, the electronic clock because of its low price, eas
decode38
- 编码器38代码，FPGA实现，语言Verilog编写-Encoder 38 code, FPGA implementation, language Verilog prepared
bios44Source
- arm的bios烧写源程序-arm burning source of bios
stl_eVC
- EVC Programming Microsoft Windows CE Dot NET 代码: 主要内容： 一共23章，EVC下编程源代码-EVC Programming Microsoft Windows CE Dot N ET Code : main elements : a total of 23 chapters under EVC programming source code
LPC2138_FRE
- 基于LPC2138的频率计，内部自生成PWM用于测试-LPC2138-based frequency meter, for testing the internal self-generated PWM
Project_1
- 飞思卡尔公司HC12系列单片机Mc9S12xs128,液晶1602驱动程序，48MHz主频，亲测可用-Freescale HC12 family of microcontrollers Mc9S12xs128, 1602 LCD driver, 48MHz frequency, pro-test available
using-the-gate-light-up-an-LED-lamp
- using the gate light up an LED lamp-Experiment 1 a: using the gate light up an LED lamp
wireless_FPGAcode
- 无线通信模块设计FPGA代码 包括matlab模型文件及verilog源代码-The wireless communication module design including FPGA code matlab verilog model file and source code