资源列表
Nov22_11
- vhdl code related to mp3 decoder with some test benchs
pwm
- 基于TI公司的tms2812pwm波形测试-Based on TI tms2812pwm waveform test
STM32_LED_TEST
- 适合初学者对STM32芯片GPIO的认识，入门级-This example describes how to use GPIO BSRR (Port bit set/reset register) and BRR (Port bit reset register) for IO toggling. These registers allow modifying only one or several GPIO pins in a single atomic write access
Nand_Tools
- WRITTING Nand FLASH Tools
lariviere2008uclinux
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
ADC0832.rar
- 用FPGA控制DAC0832，实现锯齿波的产生，里面有详细介绍，有连接方法和程序，还有0832的资料。,FPGA control with DAC0832, saw the emergence of the realization, which is detailed, there are methods and procedures to connect, there are 0832 data.
C6678 bootloader
- TI最新多核DSP TMS320C6678的引导程序
C6678_pg10_bootloader
- C6678 DSP的bootloader-C6678 DSP bootloader
Verilog-Design
- 包括三个文档: 1.基于Altera Quartus II 的模块化设计应用 2.基于Xilinx ISE的的模块化设计示例 3.模块化设计方法的设计流程-Consists of three documents: 1. Based on Altera Quartus II modular design applications 2. Xilinx ISE based on the modular design of Example 3. Modular Design for desi
cam
- 飞思卡尔电磁组程序，已经过调试和烧写，而且经过一次飞思卡尔竞赛-Freescale electromagnetic group program, has been commissioning and programming, and after a race Freescale
dpsk_3rd
- 2DPSK调制与解调。学生实验使用，包括信号源模块、时钟源生成模块、信号调制模块，信号解调模块。 其中包含了边沿触发下的阻塞语句。 编译环境：Q2 11.0，编译语言：verilog，仿真软件：moelsim altera -2DPSK modulation and demodulation. The student experiments, including the source module clock source generation module, signal modu
Edit_2
- EVC4平台下用eSuperMap开发的基于WinCE的程序，使用于导航及GIS相关应用开发和学习指导工作！-EVC4 platform developed using eSuperMap based WinCE program, used in navigation and GIS-related application development and learning to guide our work!