资源列表
7_1
- 电路端口为：异步清零输入端口rst，输入时钟clk_in，输出时钟clk_out。并分别采用两种以上的方法实现。(Frequency divider circuit port is: Asynchronous Clear input port rst, input clock clk_in, output clock clk_out. And use two or more methods to achieve.)
基于FPGA的等精度频率计的设计
- 基于FPGA的频率计，采用的方法为等精度。(Frequency meter based on FPGA)
实验2 蜂鸣器实验
- STM32 蜂鸣器实验库函数代码 控制蜂鸣器的响应(STM32 buzzer experiment library function code)
ispLEVER是LATTICE的CPLD、FPGA继承开发环境
- ispLEVER是LATTICE的CPLD、FPGA继承开发环境，ISPLEVER许可文件--ISPLEVER6.0-7.1的注册机,ispLEVER is LATTICE of CPLD, FPGA development environment succession, ISPLEVER license file- ISPLEVER6 .0-7.1 the Zhuceji
Successive-binary-adder
- Quartus环境下的逐次进位加法器的编写代码，适合初学数字逻辑设计的学习-Successive binary adder in Quartus
ActelFPGA_RAM_an
- FPGA下开发RAM的手册，与FPGA自带的说明不同-FPGA development manual of RAM, comes with instructions and FPGA
DSP[2]
- 这都是DSP的程序，希望大家可以用的上-DSP procedures in the hope that we can use on the
EDAshiyanbaogao
- 关于VHDL的关于数字跑表的eda的课程设计！-failed to translate
VHDL_ALTERA_Max-EPM570-BELL
- ALTERA MAX-II-EPM570 VHDL Source code Bell , shematic 21EDA-ALTERA MAX-II-EPM570 VHDL Source code Bell , shematic 21EDA
3
- MINI STM32开发板例程之串口实验-MINI STM32 example3
LchmQuartus
- VHDL LCHM signal Quartus 90.
pwm_timer
- PWM和Timer的FPGA实现，文档代码齐全。-PWM and Timer for FPGA implementation, documentation, code complete.