资源列表
AD0_INT
- 周立功的nxp lpc1114adc转换例程 中断模式转换模式 内含串口通信 adc转换-zlg nxp lpc1114adc conversion routines interrupt mode conversion mode adc conversion includes serial communication
shexiangtoujiandankepao
- 摄像头简单可跑程序，与大家分享。不求贡献-Camera can run a simple program to share with you. Thank you
3.2.7_REL
- DM9000AEP WinCE 驱动源代码。-DM9000AEP WinCE driver source code.
AD_lpc17xx
- 开发工具KEIL MDK，LPC17XX环境下AD转换的驱动例程。-Development tools KEIL MDK, under LPC17XX environment AD conversion driver routines.
ISD1800
- 标准字库资料 液晶显示资料 GT21L16S1W字库芯片.pdf-Standard dictionaries material
quartus0modelsim0simulation
- quartus用modelsim仿真.pdf 内容不错，乘法实用-using modelsim for quartus simulation
GPS-GPZDA
- 随着通信技术的迅速发展，为适应社会的需求，满足用户的需要，必须提高软件开发水平，近些年随着嵌入式操作系统的兴起，嵌入式终端与GPS的结合更加完善了GPS的可视性、功能性和操作性，使GPS的泛用性得到增强，用户的数量增多使功能需求越来越复杂，其中就有部分用户对时间精度要求较高，需要专门的语句格式来解析，这也是GPZDA得到应用并推广的原因之一。-With the rapid development of communications technology in order to meet the
uCOSII_KeilC
- ucosII在51上的移植，使用KEIL-ucosII transplantation in the 51' s, the use of KEIL
sm
- This example shows how a Sm component is directly coded in VHDL as concurrent statements. The multiplexor is coded as a single "when" statement. "Sm" is mnemonic for subtractor-multiplexor.
TimerRITadc
- RTC read adc data实时读取ADC数值-RTC read adc data
mul_ser12
- 本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。-The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.
sdram_controller
- 该模块是一个基于FPGA的SDRAM控制器，该模块有两个接口，一个接口是系统接口，一个连接SDRAM的接口。可以适应不同速度和带宽的SDRAM。-This application note describes the design of a FPGA SDRAM controller.The controller has a system interface on one side and a SDRAM controller for two 16 MB SDRAMs on the other