资源列表
counter
- Counter for VHDL Project
PWM
- PWM Generator Using DSPIC30F4011
signaddsub12
- vhdl coding for signed adder substractor
counter
- vhdl code for a simple counter
ps
- vhdl code to change the bits stream from parallel to serial
multiplier
- 压缩的乘法器。是基于VERILOG 语言实现的，有较快的速度。-Compression of the multiplier. Is based on the VERILOG language, there is a faster speed.
1
- 利用单片机来驱动液晶显示，使液晶能显示自己想要的内容。-Single-chip computer to drive the liquid crystal display, the LCD can display the content they want.
dualport
- dual port sram test programe-sram test
cascaded-muliplier
- Verilog based for cascaded multiplier design-Verilog based for cascaded multiplier design
AntGlitch
- 运用VHDL语言，实现脉冲采集的滤波子程序，利用打两拍进行毛刺滤波，可以将该子模块加载到主程序中。-The use of the VHDL language, to achieve the the pulse collected filtering subroutine utilize playing two beats glitch filtering, the sub module is loaded into the main program.
TimeOutCounter
- 用于FPGA内部计数辅助DDR操作，便于开发-TimeOut Counter
LP-FIR-filter-design-rectangular-window
- LP FIR filter design rectangular window