资源列表
BCD_to_Excess_3b
- BCA code are exchanged to excess 3
syncount
- synchronous counter in verilog
dds
- 高精度高速正弦波生成，正弦波相位和正弦波频率可调。-make sin
PS2_Controller
- verilog hdl 实现的PS2控制模块-verilog hdl PS2
MUX
- VHDL Code for 4:1,2:1 MUX using when statment
music.v
- 用VHDL硬件描述语言在CPLD实现播放音乐-VHDL hardware descr iption language used for playing music in the CPLD
CIRCULAR.CPP
- This a DSp program enjoy-This is a DSp program enjoy
spi_slave
- SPI的verilog源代码，可以和DSP2812通信，已经试过，可行。-SPI verilog source code
fp_adder
- FP affer 32bit vhdl code from an old project
key
- 实现FPGA 按键控制部分代码，FPGA芯片采用xilinx sptan3e 可以实现按下按键后FPGA通过max232给电脑发送数据-Achieve FPGA button control part of the code, the FPGA chip using xilinx sptan3e can realize after press the button the FPGA through max232 send data to a computer
sketch_mar24a
- 基于Arduino 小车的蓝牙控制代码。-Arduino Bluetooth car control code.
1wire
- this faile is the interesting