资源列表
analog.c
- jfwletjwevmyrejemrukrk iptyik 67koi
CLK_DIV
- verilog HDL写的时钟通用计数分频程序，设置系统时钟，并根据目标时钟，设置分频系数即可得到目标时钟。已实际测试可用。-verilog HDL write clock common procedures for the count and divide, set the system clock, and the root According to the target clock, set the frequency division factor can get the targ
uart_trs_state
- 本程序是串口的FPGA产生程序，希望在此能够给与大家共享-This program is a serial FPGA generator, I hope to give everyone shared this
signal_example5_c
- C example code for signal Macros by c/c++.
base-of-51
- 在数码管上实现0——60循环显示数字，每秒加一-In the digital tube to achieve 0- 60 cycles for display numbers, plus a second
fulladder
- this is fulladder 1bit with testbench
pwm
- 使用VHDL实现可调的PWM控制器，便于初学者学习-Use VHDL to achieve an adjustable PWM controller, easy for beginners to learn
stm32_time
- stm32实现精确定时源代码，经过验证，可实现-stm32 accurate source code from time to time, after verification, can be realized
main
- Used to display a hexadecimal value in 7 segment LED display using an interrupt in PORTB upper 4 bits.
main
- MSP430F449的定时器中断的应用，本程序来源于TI官方提供。对初学者很有帮助。-MSP430F449 timer interrupts the application of this program from TI from official sources. Very helpful for beginners.
CLOCK_2
- 用汇编实现C51链接的数码管时钟功能显示，有时分秒和天数- Realizes the C51 link nixietube clock function with the assembly to demonstrate, sometimes minutes and seconds and number of days