资源列表
CC2530_DS18B20
- CC2530 驱动DS18B20的演示程序，已经可以调通，供大家参考-CC2530 driver DS18B20 demonstration program, already transferred through, for your reference
english
- 一个proteus上画的电路图 简单的最小系统的实现 复位电路 包括按键复位和上电复位 -A proteus schematic draw The implementation of the minimum system Reset circuit Button reset and power-on reset
spi
- spi原理的详细说明及verilog实现(SPI principle and its implemetation in verilog HDL)
fsm
- 有限状态机fsm 二段式编写 verilog(Finite state machine, FSM, two sections, verilog)
ANDOR
- copuertas logicas and or
实验1
- 用verilog语言实现译码器,包含数据流文件(Achieve decoder with verilog language, including experimental data stream file)
Chapter4
- MIPS is a reduced instruction set computer (RISC) instruction set architecture (ISA)[1]:A-1[2]:19 developed by MIPS Technologies (formerly MIPS Computer Systems). The early MIPS architectures were 32-bit, with 64-bit versions added later.
counter
- 1. 支持递增/递减/增减可配置 2. 支持计数器使能可配置 3. 支持8位计数器(Add mode, subtraction, add and subtract mode, hold mode)
2bit_ecc
- 基于BCH码的ECC纠错算法，可纠错2位错误码，供参考(Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.)
programme stabilite
- fbdhtg gfngnhgf j mn nmj,m vgvcx
dayashankar_nair_verilog_2.2.tar
- finite state machine
counter
- 基于FPGA平台的，计数器的简单实现过程(Code based on FPGA, a realization of VHDL/counter)