资源列表
alu
- verilog编写的alu模块-Verilog modules prepared by the ALU
create-mutex
- ucos-ii中互斥信号mutex建立源码-ucos-ii in the establishment of mutually exclusive mutex signal source
DSP_REALTIME
- DSP算法（ANSI_C） PROGRAM TO DEMONSTRATE REAL TIME FILTERING USING fir_filter() AND iir_filter() -DSP algorithm (ANSI_C) PROGRAM TO DEMONSTRATE REAL TIME FILTERING USING fir_filter () AND iir_filter ()
unishift
- An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
avr.tar
- ucos rtos task for led blinking by each task using suspend and resume method
i2c_wreg
- i2c 功能写操作源代码，供大家参考一下，软件上已经编译OK-i2c write function of the source code for your reference, the software has been compiled OK
frequency-divider
- anything frequency divider-frequency divider
uart
- Verilog 编写全双工UART input clk, // 这个模块的主时钟 input rst, // 同步复位信号 input rx, // 串口接收端口 output tx, // 串口发射端口 input transmit, // 发送信号 input [7:0] tx_byte, // 发送的字节 output received, // 表明，已接受到一个字节 output [7:0] rx_
US020Testprogram
- 超声波模块驱动程序，兼容51系列单片机，可直接移植哦-Ultrasonic module driver compatible with the 51 series, can be directly transplanted Oh
ditong
- DSP写的低通滤波，每60个数去一下平均数，前面加一个数后面减一个数，总是60个数的平均值，验证好用。-DSP write low-pass filter, go to the average number of every 60, preceded by a number less behind a number, the average number is always 60, verification use.
ADC
- Chip type : ATmega48V Clock frequency : 1.000000 MHz Memory model : Small External SRAM size : 0 Data Stack size : 128 ADC10检测值由URAT输出-Chip type : ATmega48V Clock frequency : 1.000000 MHz Memory model : Small Exte
Verilog-code-for-finding-GCD
- State machine implemented in verilog to find GCD of two 8 bit numbers. Two files are included (module and its testbench)