资源列表
traffic
- ＣＰＬ串口程序经过调试希望大家喜欢，很好呀大家慢慢来下载吧-CPL after serial debugging procedures hope you like, ah well we slowly download it
fpgaad7865
- 用FPGA控制AD7865的控制逻辑，状态机-AD7865 control logic
PC8501
- 本程序为Verlog语言程序，采用QUARTUS6.0编写，程序实现的功能是控制AD2S80的转换和和数据总线上数据的读取-This program is Verlog language program, using QUARTUS6.0 preparation, program implementation function is to control the conversion and AD2S80 and data bus to read data
MAIN
- this a file used for the spi communication between spi1 and spi2 of dspic30f6014. this is the main file which is heart of this project.-this is a file used for the spi communication between spi1 and spi2 of dspic30f6014. this is the main file
BootTraps
- AVRco - Pascal Example Code
fast_antilog_latest.tar
- Anti-Logarithm (square-root), base-2, single-cycle
UART
- Verilog编写的UART模块,波特率19200，系统时钟100MHz,x3s50an应用成功-UART module using Verilog
Relay-control
- 该代码是继电器控制的汇编程序，在简单的单片机最小系统上即可实现对继电器的控制-This code is relay control assembly program, in simple single chip minimize system to relay of the control can be realized
ahb_master
- ahb master 文件，主要是ahb发数据-ahb master file
DSP
- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001 VHDL Data-Flow modeling KEYWORD: generate, array, range, constant and subtype- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001
at24c02
- STM32 点 24c02 源码开发，可以参考进行项目开发-STM32 point 24c02 source development, you can refer to the project development
PCNN FPGA
- 用VHDL语言写的PCNN一个神经元的工作机制