- BoxD 一维数据的盒维算法
- ADCcalibrationV11 This example program runs from RAM on the EzDSP. It initializes the event manager to generate a periodic start of conversion (SOC) pulse to the ADC. This will trigger a conversion of the ADC and when completed the ADC will generate an interrupt. The interrupt is serviced and the ADC calibration function is called. This function will read two user selected reference channels and calculate the appropriate calibration gain and offset and then calibrate all other user channels.
- CodeSoftServer 一个使用CodeSoft类
- testssl.sh-2.9dev testSSL source code included
资源列表
rushing
- A six people s rushing replies an implement, use some s switches in toggle switch K0 ~ K5 is that ON accomplishes when rushing to reply button , nobody rush to answer, 6 numerical code circulation takes turns at demonstrating 1 ~ 6 (horse races) , wh
1602_c
- LCD1602的程序，该液晶与LCD1601差不多，只是比LCD1602多一行，该液晶在应用中比较常用
BMO
- 跑马机程序 自动工作
Serial-S3C44B0
- flash serial input queue. returns 0 on success or negative error * number otherwise-flash serial input queue. 0 succeeded the returns on ess or negative error number otherwise *
FLASH_OP
- uPSD3200FLASH汇编编程参考设计.zip
24C08
- 使用24C08芯片，实现多花样流水灯实验。-24C08 multi-pattern light water experiment
vg
- 通过vhdl编程实现利用vga显示横向、纵向的彩条码。和棋盘形码-By vhdl programming the vga display horizontal and vertical color bar code. And board barcode
serialtoparellel
- 很好的串口转换程序，很好用。都试过，跑过很多遍，而且已经应用在产品设计中-Serial conversion process very good, very good. Tried everything, ran many times, but has been applied in product design
spislave1
- SPI slave communication
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
testHDLADJ64M
- 64k 帧头的猫述与实现，以及帧的误判以及相关的处理办法-64k header cat references and implementation, as well as false positives and the associated frame approach
FSM
- 用verilog语言编写的FSM文件，有限个状态及在这些状态之间的转移和动作等行为的数学模型，在计算机领域有着广泛的应用。-Mathematical model with verilog language FSM file transfer and finite number of states and actions between these states and other behavior in the computer industry has a wide range of appl