资源列表
X2504345
- One for the external microcontroller to see the door x2502345 c-language program-A BCD conversion software for the microcontroller, 16-hex BCD conversion software
pwm
- 控释电机调速，pwm生成，控释正反转，且可以加速减速
ADC124
- 采用verilog编写的高速串型AD采集芯片adc124驱动代码，占用le较少，效率高，目前我应用在较多产品上-Verilog prepared using high-speed string-type AD Acquisition chip adc124 driver code, occupation le small, high efficiency, the current I applied to more products
music1
- VHDL 多功能数字钟源码音乐模块2，自扒简谱-Multi-function digital clock source VHDL music module 2, since the expense of musical notation
pipe
- pipe lining.It is based on multiple pipe lining.Pipe lining concept utilized in processors.
fpga-5
- Design a “Bouncing Picture” which can bounce on the border of the monitor.
The-Serial-communication-
- 随着多微机系统的应用和微机网络的发展，通信功能越来越显得重要。串行通信是在一根传输线上一位一位地传送信息.这根线既作数据线又作联络线。串行通信作为一种主要的通信方式，由于所用的传输线少，并且可以借助现存的电话网进行信息传送，因此特别适合于远距离传送。在串行传输中，通信双方都按通信协议进行，所谓通信协议是指通信双方的一种约定。约定对数据格式、同步方式、传送速度、传送步骤、纠错方式以及控制字符定义等问题做出统一规定，通信双方必须共同遵守。-With the application of multi-
PANKAJ
- THIS THE SOURCE CODE FOR LIFT BY VHDL
bujindianji
- 改程序为步进电机定位控制系统VHDL程序。-Stepper motor positioning control system VHDL program.
pid_grando
- 基于IQmath的PID增量式算法实现，适用于所有的TI C2000系列DSP，可直接使用。-The PID IQmath incremental algorithm based on IQmath, applicable to all TI C2000 series DSP, can be used directly.
TIMER1
- generate the interrupt each 1 ms
uart_tx
- 基于verilog的uart发送模块，具有可选择的奇偶校验功能，经过modelsim仿真可用。-Based on the uart verilog transmit module with selectable parity function, available through modelsim simulation.