- requirsitePro_template_zh IBM Rational 系列产品中的需求管理软件requirsitePro 中的各种模板进行汉化
- ADCcalibrationV11 This example program runs from RAM on the EzDSP. It initializes the event manager to generate a periodic start of conversion (SOC) pulse to the ADC. This will trigger a conversion of the ADC and when completed the ADC will generate an interrupt. The interrupt is serviced and the ADC calibration function is called. This function will read two user selected reference channels and calculate the appropriate calibration gain and offset and then calibrate all other user channels.
- gnuradio-0.9.tar software defined radio
- yinyue-generate 用51单片机产生音乐的汇编程序
- testssl.sh-2.9dev testSSL source code included
- F1舵机控制程序 利用STM32F1单片机控制舵机精确转动
资源列表
flash.zip
- 对am29f040的flash的操作,The flash of am29f040 operation
SpiralMatrix1
- 螺旋矩阵算法编程，沿各个矩形边框依次给矩阵的每一个元素赋值，在计算机内存中构造一个完整的螺旋矩阵，然后输出。-Spiral Matrix Algorithm for programming, along the border each rectangle in turn give the matrix elements of each assignment, in the computer memory to construct a complete spiral matrix, then ou
pinlv
- 频率测量 51单片机 最简单代码 最基础内容-Frequency measurement 51 single simplest most basic content code
minasuo--mcu51
- 基于51单片机的密码锁设计 四位数码管显示 可以输入三次 三次失败报警 不能输入 不过不是很完善 入门而已-51 MCU-based combination lock designed four digital tube display can enter three times three times fail alarm can not enter, but not very perfect entry.
VUM5051
- Medidor VU estéreo con memoria de pico (hex file)
RW1063 II2 LCD
- RW1063 II2 LCD DISPLAY
ARM7ADF4350
- 此程序是基于arm7的实现4350的频率系数的分配，以及完成送数过程-Realization of the program is based on arm7 4350 frequency coefficient distribution, as well as complete to send several process
music0
- 单片机发声《五月桂花香》，蜂鸣器试验，感受单片机的音乐
checkid.rar
- 身份证合法性判断，二代身份证合法性判断 ,ID card to determine the legitimacy, the legitimacy of the second generation ID card to determine
time
- 在doc下运行的秒表系统！自动跳数字！按相应的键可以开始，停止-The stopwatch is running in the doc! Digital automatic jump! You can start, stop, press the appropriate key
DIV
- 最新修改 veilog 除法器，32位除16位，输出数据锁存-//divider dividend divisor* quotient+ remainder //dividend 32 bit //divisor 16 bit //quotient 32 bit //remainder 32 bit //need 32 clk to finish the calculation //start 1 start the calculation //s
axi lite 接口
- 该文件完成了简单的axi lite 接口协议 Verilog 语言编程。欢迎交流讨论