资源列表
lvbo
- 10种软件滤波的方法 值得一看 非常好的资料-10 kinds of filtering software, a very good way to see information
TimerMode_PWM
- he LPC932 can be used to create a Pulse Width Modulated PWM signal. That s an analog signal, with only 2 discrete levels, for example 0V and 5V and a constant period. The current value of this signal at a certain poiTnt of time is proportional to its
EV_TIME1_1MS
- 利用DSP EV模块实现1ms延时程序，需根据具体使用时钟频率 -use DSP Module 1ms delay procedures required under the specific use of the clock frequency
verilog
- 一个简单状态机的.v文件，含testbench
srbjq
- vhdl实现的三人表决器，大家一起交流一下，-VHDL realization of three voting machines and we can work together to exchange about
clock
- verilog数字钟 Verilog HDL 写的不是很好,有好的就不要下我的了-verilog clock
PPM_Coder
- PPM 编码器 按照PPM编码格式编写的普通VHDL代码-PPM PPM encoder encoding format prepared in accordance with the ordinary VHDL code
MSP430F552x_adc_02
- MSP430F5 ad转换单词多通道转换-MSP430F5 ad words conversion of multi-channel conversion
spitst
- SPI interface using 8051 programmed in embedded c
sRAM
- FPGA与Sram通信并液晶显示，程序为verilog语言-FPGA and Sram communication and LCD, the program for the verilog language
LED_DSP
- 一個在DSP上開發的簡單範例, 用來控制DSP上面的LED燈, 隨著按某個按鈕, 就會讓相對應的LED閃起來-One on the DSP development of a simple example of the above is used to control the DSP LED lights, with the press of a button, it will make the corresponding LED flashes up
sync_fifo
- 同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.