资源列表
RS485
- 以泓格7188为数据采集模块的RS485网络,由于所连接设备的产品性能或其他问题容易出现数据传输的不稳定性,本算法对嵌入式模块 的程序设计具有通用性，其基本原理可以广泛使用。
bingxingjiafa
- 用vhdl语言 来实现 四位并行加法器的功能 是本科生的必学内容
eda.rar
- 使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟,The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock
ex1c
- This file is distributed in the hope that it will be useful, but WITHOUT * WARRANTY OF ANY KIND. * * Author(s): Ole Saether * * DEscr iptION: * * Hello World program. Please note that this program runs the internal 8051 * on t
key_main
- TMS320F2812 DSP的键盘接口程序！仅供参考！-TMS320F2812 DSP keyboard interface program! For reference only!
Clock_gen
- Vhdl clock generation Example source Input Clock 96Mhz Generated clock1 is Positive 300Khz clock & clock1 is Negative 300Khz clock -Vhdl clock generation Example source Input Clock 96Mhz Generated clock1 is Positive 300Khz clock & c
partiy-generator
- hi this is vhdl code for parity generator/checker
FSK
- FSK 的FPGA实现，使用verilogHDL语言-FSK in FPGA,using verilogHDL
1602
- LCD1602的Ｃ程序，简单的基本显示字符串，包括写地址，写数据等-LCD1602 driver
MVDR_with_interference
- an example for MVDR with interference
IQ_sin_cos_mod
- Cordic根据输入的IQ正交两路信号求取对应的正切值-Cordic according to input the IQ of orthogonal signal to calculate the corresponding tangent value two road
lcdct
- at070tn83驱动 驱动 驱动 -driver of the lcd