资源列表
dds-design
- * DEscr iptION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DEscr iptION : DDS BY PLD design Online. * * AUTHOR : Sun Yu * * HISTORY : 12/06/2002 *
12_convert
- convert.vhd 本例是从程序包中提取出来的，不能单独编译-convert.vhd the cases from the package is extracted, not separate compiler
Params
- SDRAM控制器Verilog员代码，设计参数模块，整个模块的所有参数定义-SDRAM controller member Verilog code, design parameter module, the entire module of all parameters defined
xuanlvbo
- 数字图像处理中有许多种滤波方法，本方法是一种特殊的方法，即旋律波，有比较明显的效果-xianlvbo
show1234
- ：在四个七段LED数码管上显示数字“1234”-: In the four seven-segment LED digital display the number " 1234"
sp706
- 硬件看门狗程序，用在ATMEGA128上，包括芯片内部看门狗，和外部硬件看门都sp706-dware watchdog program, used in ATMEGA128, including the chip internal watchdog, and external hardware janitor sp706
my_fir
- Verilog 写的FIR滤波器，modelsim仿真通过-Verilog write FIR filter, modelsim simulation through
suanfa
- 通过移位和类型转换 将FPGA的DA输出和AD输入转换为对应LCD12864在屏幕上对应的点-Shift and type conversion through the FPGA DA output and AD input is converted to the corresponding LCD12864 corresponding point on the screen
aic23_loopback
- dsp 语音信号编码解码 PCM编码 ALaw压缩解压缩方法的运算-dsp codec PCM encoded voice signal compression and decompression method ALaw computing
IRtest
- 红外遥控测试程序,简单的译码.可用在各种红外遥控器中.-Infrared remote test procedure, a simple decoding. Used in a variety of infrared remote control.
TimerB7
- msp430F149,说明：拨动P3.4使用软件和TB_0 ISR。切换每50000 SMCLK周期。 SMCLK时钟源TBCLK。-Descr iption: Toggle P3.4 using software and TB_0 ISR. Toggles every 50000 SMCLK cycles. SMCLK provides clock source for TBCLK.
pid
- It is a verilog code for a vedic multiplier using a barrel shifter