资源列表
count64
- 将5MHz时钟信号分频后得到1.6/3.2秒可选的同步信号，还可接外接同步信号对其进行强制同步-To 5MHz frequency clock signal 1.6/3.2 seconds after the optional sync signal, external sync signal can then be forced synchronization
4_bit_parallel_add-sub
- 4 bit parallel add-sub with test bench.. in vhdl-4 bit parallel add-sub with test bench.. in vhdl..
encoder
- here aach ed h e sh if\er m\odupl€ e
CLK_DIV_N
- 对输入的时钟进行分频输出:输出频率＝ 输入频率/(2*N+2-Of the input clock frequency output: Output frequency = Input frequency/(2* N+2
12
- cordic algorithm using verilog code
motor-control
- 可逆计数器，有多重用途，可独立应用，亦可作为系统的一个模块！使用方便，-cycle count
touchpanel
- Touch panel sample code-Touch panel sample code..
0809
- 0809的vhdl程序，0809的8位转换数据输出，便于初学者学习-Vhdl program of 0809, 0809 8 conversion data output, easy for beginners to learn
Key-input-module
- 基于altera器件的按键输入模块verilog-Based on altera device key input module verilog
BayesShrink_RGB
- wienerfilter for image
shine
- ARM7 Leil+ Protuous LPC2138 跑马灯造型设计-Marquee LPC2138 design
can1_model
- DSP2812 and fpga 控制 SJA1-DSP2812 and fpga control procedures SJA1000