资源列表
DSP_SMOOTH
- DSP算法 SMOOTH: CONVOLVES A MATRIX WITH A 3X3 GAUSSIAN FILTER KERNEL-DSP algorithm SMOOTH: CONVOLVES A MATRIX WITH A 3X3 GAUSSIAN FILTER KERNEL
instmemory
- Instruction memory in VHDL
uart_rx
- Universal Asyncronos Received Transmitter
complex_mult
- Complex mult in vhdl
cordic
- CORDIC algorithm VHDL FPGA
shape
- 实现梯形滤波，对于输入为指数函数的类型。希望能够对你有帮助-tixing filter。hoping it will do help to you.
Analog-to-digital-converter
- 模数转化器，64位双精度的模拟输入值，16位数字输出-Analog to digital converter, 64-bit double-precision analog inputs, 16 digital outputs
shift_detector
- shift detector for altera
ram_dp_sr_sw.v
- this is a verilog source code for Dual Port RAM Synchronous Read/Write.
miaobiao
- verilog 的 48M频 出入秒表，带停止启动 清零功能-the verilog of 48M frequency of access stopwatch, with stop start clearing the
ad_ctr
- 本人编写的ad9280控制器程序，经过硬件测试通过，欢迎大家下载学习。-I prepared ad9280 controller program, after the hardware test, welcome to download the study.
UART_LED_FND_LCD
- Hi, This Verilog practice code-Hi, This is Verilog practice code