资源列表
16szxgq
- 16位数字相关器，通过4个4位相关器和两级加法电路组成
RASAsynchronous.rar
- RAS异步拨号连接程序，实现拨号连接的功能,Asynchronous RAS dial-up connection procedure, the functions of a dial-up connection implementation
fft64
- DSP 2812的 64点fft的C程序-2812 proceedings of the 64-point fft
read_signals
- 了解DSP 开发系统和计算机与目标系统的连接方法-Understanding of DSP development system and the computer system, connection method and the target
main
- 语音信号的A率（或u率）压缩算法1.本试验要求完成的内容是使用AD将外部语音信号采集，DSP对语音信号保存处理，经过DA将处理后的语音信号输出；DSP对语音信号的处理包括A律和 律压缩解压、声音信号的音效处理等。-A rate of voice signals (or u rate) compression algorithm 1. The complete contents of the test requirements is the use of AD to an external aud
door_state
- 实现自动门的控制,实现其开、关、复位、门开最大、门关最小等功能-Realization of automatic control
binary_to_BCD
- 本人编写的2进制转换为BCD码的verilog程序，绝对可用，已测试通过。-I write binary to BCD verilog program, absolutely free, have been tested.
counter
- 脉冲上升或下降沿个数计数功能，并且可以配置初态和触发计数条件-Pulse rise or fall along a counting function, and can be configured to initial and trigger conditions
cmi-decode
- cmi decoder,veilog代码，已验证-cmi decoder, veilog code has been verified
shifter2
- 改进型桶式循环移位器，用VHDL实现，经时序仿真测试正确-modified barrel cyclic shifter by vhdl
synd
- Syndrome calculator basic unit for reed solomon decoder in verilog language
hmwk3try.vhd
- Design a circuit that take three N-Bit binary numbers as inputs and calculate the average of the largest number and the smallest number as the output. Note that the length of the input numbers should be defined variable