资源列表
count
- 自己编制的计数器的verilog代码 希望能对大家有所帮助
sseg
- vhdl codefor 7 segment display
radar_pulse_freq
- 对雷达的脉冲全景图部分进行编写的DSP程序,主要使用Ｃ语言实现的算法 -Panorama of the radar pulses DSP program written in part, the main algorithm using C language
main
- timer 0 used for pwm generation
fir_lp
- 1. To design FIR filters in MATLAB to achieve various types of frequency selectivity, e.g., lowpass, highpass，bandpass, etc 2. To verify the frequency response of the designed filters in MATLAB 3. To implement the designed FIR filters using C67
IIC
- FPGA实现IIC读写功能，用NIOSII软核实现-FPGA implementation IIC read and write capabilities, soft-core implementations with NIOSII
BJDJ_19
- 步进电机控制设计，读取显示器上显示的正、反转命令，转速（16级）和转动步数后执行，转动步数减为零时停止转动。-The stepper motor control design, the positive and reverse commands displayed on the display is read, executed after the speed (16) and the rotation step number, and stops rotating when the rotat
uart
- uart模块，用于串口开发使用。简单易懂！-uart module for serial development and use
basedon_mega128_rs232
- 自己调试成功的基于mega128单片机与pc通信的rs232通信的程序 -a rs232 code with mega128 to communicate wiht pc
7135
- 基于ATmega128的ICL7135驱动程序-ICL7135 based ATmega128 driver
FIR-filter-design-LP-triangular-design
- FIR filter design LP triangular design
CCSv5-China-University-Site_License
- ti官方给各个大学ccs在中国区的认证license，有了这个文件可就可以在中国任意使用注册的ccs啦。-Ti official to the various universities ccs certification in China license, with this document can be used in any Chinese registered ccs friends.