资源列表
dsplab-C
- 2047经典实验测试程序,适合初学者使用，代码完整可以直接使用-2047 classic experimental test program, suitable for beginners to use, the code integrity can be used directly
Oscilloscope
- The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware.
Filter-Wiz-PRO-3.2aCrack
- 本人使用次数最多的分立元件滤波器软件,功能非常齐全,基本能想到的问题它都替你考虑到了,唯一缺点是不注册的话对极点数和阻值作了一定的限制-I have the highest number of discrete components using filter software is very complete, it can basically think of the problem are taken into account for you, the only drawback is no
RTOS
- 各位C51的爱好者能够看到我的拙作，这离不开龙 啸九天版主的支持，在此，我向他表示感谢，也相信C51BBS会越办越好！-C51 fan you can see my apology, which is inseparable from Long Xiao nine moderator support in this, I thanked him, and believe C51BBS will be better and better!
abcd_58049
- verilog 时钟 整点报时 广播报时 自主调节定时报 闹钟设置-verilog clock
200851911363
- 东进语言卡开发的详细例子，这个是电话银行的例子-East of the detailed development of the language card examples, this is the example of telephone banking
MST705_4.3PCODE
- LED液晶屏驱动芯片MST705 驱动4.3寸屏C源码。- LED LCD driver chip MST705 drive 4.3-inch screen C source code.
PpcPKISD
- 基于ppc的PKI_SD的一个小模块，通过远程调用获取SD 卡中的数据
PWM-control-2
- 总之，PWM既经济、节约空间、抗噪性能强，是一种值得广大工程师在许多设计应用中使用的有效技术。-In short, PWM already economy, save space, robust performance is strong, is a kind of worth the engineer in many design application of technology used in effective.
FilterWizPRO3.2.rar
- 这是两个软件的压缩,其中一个件的功能是实现滤波器的设计,名为"Filter Wiz PRO 3.2" 另一个是这个软件的破解安装程序,因为此软件是收费的,用破解板出来的电路图,建议亲自搭建,以证正确与否.,These are two of the compression software, one of which is to achieve the function of pieces of filter design, called " Filter Wiz PRO 3.2&quo
500Hz_80Hzlp_410sn_DSP-V1.2
- 基于STM32F047的uVision工程文件。可以实现实时从ADS1299采集数据并传递到微处理器低通滤波。实现了嵌入式实时数据采集系统采集滤波等的预处理部分的功能。-Based STM32F047 of uVision project file. You can achieve real-time data collection the ADS1299 and transmitted to the microprocessor low-pass filter. To achieve a p
jiarao4
- 加扰与解扰，VHDL实现。初始寄存器值为1产生的m序列。-Scrambling and descrambling, VHDL. Initial register value 1 of the m-sequences generated.