资源列表
AVR_fighter
- 51/AVR单片机HEX文件下载上位机软件-AVR_fighter
UCOS_word
- 详细介绍ucos安装、实时系统、内核结构、任务管理、时间管理、任务间通讯和同步、内存管理、移植ucos等。-Details ucos installation, real-time system, the kernel structure, task management, time management, communication and synchronization between tasks, memory management, portable ucos and so on.
stm32-LCd
- ARM Cortex M3和迪文DMT32240S035_01WT的连接与编程指南-ARM Cortex M3, and Devin DMT32240S035_01WT connection with the Programming Guide
NCO
- 关于FPGA设计实现NCO，包括查找表法和CORDIC算法的改进-FPGA design and implementation on the NCO, including the look-up table method and the CORDIC Algorithm
FPGA_and_CPLD_VHDL_GB
- VHDL数字电路设计的电子书，很好的学习材料-VHDL digital circuit design of e-books, very good learning materials
omapl138
- The OMAP-L138 C6-Integra™ DSP+ARM® processor is a low-power applications processor based on an ARM926EJ-S™ and a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.-The
verilog
- verilog的一些源代码，包括8051核的实现，i2c总线的实现等源码
bldc-pID
- bldc采用霍尔效应传感器通过ecap捕获转速 PWM调节电压 PID闭环调速-bldc using Hall effect sensor PWM voltage regulator PID loop speed control via ecap capture speed
Fpga_And_Cpld
- Fpga_And_Cpld设计经验总结，在数字电路的设计中，时序设计是一个系统性能的主要标志，在高层次设计方法中，对时序控制的抽象度也相应提高，因此在设计中较难把握，但在理解RTL电路时序模型的基础上，采用合理的设计方法在设计复杂数字系统是行之有效的，通过许多设计实例证明采用这种方式可以使电路的后仿真通过率大大提高，并且系统的工作频率可以达到一个较高水平。-In digital circuit design, timing design is a main indicator of system
FPGA
- FPGACPLD数字电路设计经验分享，CPLD digitalcircuitdesignexperiencetoshare-FPGACPLDdigitalcircuitdesign experiencetoshare
ADXL345
- 51单片机驱动ADXL345角度传感器的程序。已经成功运用了很久了-51 single-chip ADXL345 angle sensor driver procedures. Has been successfully used for a long time
Roclog-v5.0.17
- 该款芯片的超低功耗和良好的性能价格比使其非常适合嵌入式产品应用。 -The chip' s ultra-low power consumption and good performance and low cost make it well suited for embedded product applications.