资源列表
10_100m_ethernet-fifo
- 本源码源自于网络，采用verilog编写完成10M以太网到100M以太网的FIFO转化。-The source from the network, using verilog written 10M Ethernet 100M Ethernet FIFO conversion.
hospital
- 医院进行药品进货,划价,派单等功能的系统-Hospitals purchase drugs designated price, features such as sending a single system
ADC
- 28335 EPWM ADC采样 28335 EPWM ADC采样-28335 EPWM ADC sampling28335 EPWM ADC sampling
vhdlandc
- 单片机c语言和CPLD vhdl语言通信的程序，单片机接键盘和显示器，cpld实现电机控制脉冲，最总实现一个稳定的3维步进电机控制系统-c language work with vhdl language in controling step motor
fifo
- simulation fifo protocol
Usage_configuration_-minicom
- minicom使用tftp调试开发板配置说明，可以在linux系统中，通过串口或者USB转串口线调试嵌入式开发板。-minicom development board using tftp debug configuration instructions, you can linux system through serial or USB to serial wire debug embedded development board.
modelsim
- modelsim 使用教程,verilog或vhdl仿真-ModelSim use tutorial, verilog or VHDL simulation
temper-sample
- 这个是用ADI公司的ADU849单片机的温度采集电路板，用protel99se打开-This is the ADI company ADU849 single-chip temperature acquisition circuit board, opens with Protel99SE
S3C2410RS485communicatonexperimet
- 基于AR9 S3C2410 RS485的通信实验程序，该程序通过实验，完全满足要求-AR9 S3C2410 RS485-based communications test program through the experiment, fully meet the requirements of
shuomingsh
- 一61 板是什么开发板有什么功能 二硬件框图及简要说明 三如何利用61 板进行开发 四学习向导-shuoming
EX01_CpuTimer0
- 关于dsp定时器的设置，实现流水灯的定时的流动，-Set the timer on dsp realize the timing of the flow of light water,
LCD_1620
- MDK学习之LCD_1620.rar，祝大家学习进步！！MDK学习之LCD_1620.rar，祝大家学习进步