资源列表
elevator
- 改程序是电梯的控制程序，verilog语言编写-The reform program is the elevator control procedures, verilog language write
C8051f060_wr_interFLASH
- 对C8051f060的内部FLASH进行读写操作-Read and write operations of C8051f060 internal FLASH
dzjs51-001
- 电子竞赛单片机学习开发板Proteus仿真，帮助电子竞赛单片机初学者学习单片机-Proteus simulation the electronic contest microcontroller learning development board help the electronic contest microcontroller beginners learning microcontroller
CPLD-digital-clock-design
- 基于CPLD实验板的多功能数字钟设计，运用VHDL编写程序-Multifunction digital clock design based on CPLD experimental board, the use of VHDL programming
LED
- led小程序仅供51单片机初学者参考，小程序共享，keil中编写的。-keil
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
ADD
- Verilog编写的Altera单精度加法器源码-Altera single precision adder source Verilog prepared
E4CE40_TV_PAL
- Altera E4CE40 TV PAL制式 源码-Altera E4CE40 TV PAL standard source
ssd1963
- 一张ssd1963的原理图，已经制版，欢迎下载，不用积分的-A ssd1963 schematic has platemaking, welcome to download without integral
HalfFilterMatlab_11
- 半带滤波器的matlab设计 生成fpga所要的数据-halfband matlab
1286400
- VHDL FPGA128*64显示中文撤程序 下载试验均已成功-VHDL FPGA128* 64 display Chinese withdrawal program download trials have been successful
FFTSim.m
- 仿真FFT参数对采用FFT算法分析信号频谱的影响。产生频率分别为2Hz，2.05Hz的正弦波合成信号，采样 频率＝10Hz。根据（8-8）式，要实现分辨两个单频信号的目的，DFT的序列长度必须满足 。分别仿真3种 情况下的FFT变换：１）取 的128点数据，计算FFT；２）将128点 以补零的方式加长到512点，计算FFT； 3）取512点 ，计算FFT-fft simulation matlab