资源列表
verilog_n_evendivider
- verilog 中很好的n倍奇数分频器，开发环境为ISE10.1，仿真环境为modesim6.3-n times in good verilog odd divider, the development environment for ISE10.1, simulation environment for the modesim6.3
verilog_divdier
- veilog中的常用分频器，包括2分频 4分频 8分频等 开发环境为ise8.2-veilog commonly used in the dividers, including the 2 frequency divided by 4 divided by 8, such as development environment for ise8.2
ractor
- 虚拟仪器三涡卷蔡氏混沌吸引子设计Three scroll Chua virtual instrument design chaotic attractor-Three scroll Chua virtual instrument design chaotic attractor
keildllv1.0
- 采用visual c++实现keil的动态库详细步骤-Achieved using visual c++ dynamic library detailed steps keil
zzp
- 基于主从多机通信控制器的设计Master-slave multi-machine based on the design of communication controller-Master-slave multi-machine based on the design of communication controller
ds
- 雷达天线测试转台控制系统Table Control System radar antenna test-Table Control System radar antenna test
FPGA_statu-machine
- FPGA 编程中常用的状态机编写风格和代码。开发环境为ISE10.1.-FPGA programming state machines commonly used in writing style and code.Development environment for ISE10.1.
LCU
- 模糊Petri网在8K电力机车LCU故障诊断中的应用-Fuzzy Petri nets 8K electric locomotive in the diagnosis of LCU
adar
- 雷达智能综合测试系统Intelligent Integrated Test System Radar-Intelligent Integrated Test System Radar
system
- 发控车车载测试系统抗干扰设计anti-vehicle test system-Certain type of ground control and launch vehicle design anti-vehicle test system
system
- 气动柔性手指的位置检测系统设计Pneumatic flexible finger position detection system-Pneumatic flexible finger position detection system
ss
- 汽车载波总线的实现To achieve automotive carrier bus-To achieve automotive carrier bus