资源列表
Example-Programs
- MSC12xx series MPU Test demo source code.
test-screen
- 测试1602液晶显示屏，基于单片机系统，可以驱动和测试显示屏显示字符-1602 LCD screen test, based on single chip system that can drive and test the display shows the characters
ddr_100Mhz_2011.03.12
- 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the t
divn
- 这段代码主要实现奇数和偶数分频，这里的亮点是任意的奇数和偶数，这点在网上相关的代码不多，我主要是看了一个台湾人写的博客之后想的，希望保留，留给需要的人，因为分频在FPGA的设计中经常用到。-This code is mainly to achieve the odd and even frequency, where the highlight of any odd and even, this is the relevant code on the Internet much, I mainl
ricla0111
- ies converters and mains
adder4-7seg
- 这段程序主要是实现了两个16进制的数据相加减，主要思想是由32位的进位加法器的来。目标板是spartan 3的实验板。-This program is to achieve a two-phase addition and subtraction of data 16 hex, the main idea is to carry the 32-bit adder to. Target board is spartan 3 development board.
double_dcm
- 这个主要是在xilinx FPGA中双DCM连接的问题，这个问题网上资料很少，自己研究后并且仿真之后可以实现两个dcm的正常工作，实现倍频和时钟的反相-This is mainly the double in xilinx FPGA DCM connection problem which little information online, their own studies and simulation can be achieved after the normal work of the
ds18b20
- 采用美国DALLAS公司生产的 DS18B20可组网数字温度传感器芯片封装-DALLAS produced by the United States can DS18B20 digital temperature sensor chip package Network
sc
- 电子钟C语言程序：CPU为STC12C50S60@12M；显示部分为P1口高四位接74LS248，驱动四位红色共阴数码管（段码）P1口低四位接数码管负极（位码）；DS1302时钟芯片；-Clock C language program: CPU is STC12C50S60 @ 12M display high four part P1 port access 74LS248, drive four red common cathode LED (above code) P1 port acc
FIR2
- 以VERILOG语言描绘的用TLC549和TLC5615的数字低通滤波器的程序-VERILOG language used to describe the TLC549 and TLC5615 digital low pass filter process
3-road-Signals
- This program on 3 traffic/road signals one by one using timer.
TLC549
- 以Verilog描绘的有关于芯片TLC549的驱动程序-Described in Verilog on the driver chip TLC549