资源列表
LZY
- 基于FPGA的软FIFO代码实现，双时钟，异步。VERILOG-FPGA-based soft FIFO code, two clocks, asynchronous. VERILOG
Altera
- “Altera杯”第五届全国研究生电子设计竞赛样板-" Altera Cup" of the Fifth National Graduate Electronic Design Competition model
123
- 51单片机写的汉诺塔游戏，使用数码管显示，带自动演示-51 SCM game written by Tower of Hanoi, the use of digital control, with automatic presentation
simspark.tar
- 这是一个开源软件，simspark的凯源代码，希望对你有帮助，只是没有安装方法-It s a linux suse simspark and book it is good it should be a right book please read it and may help you wish you good luck
VHDL
- 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register w
12864
- msp430单片机控制12864液晶的程序，用IAR软件编译通过-12864 msp430 LCD MCU program, compile with the IAR software
430rs485
- msp430的rs485通信的程序，用IAR软件写的-msp430' s rs485 communication procedures, using software written in IAR
20087811328128
- 介绍MSP430单片机的C语言程序设计的资料-Introduction MSP430 microcontroller C programming language data
msp430-ad
- msp430单片机的AD转换程序，用数码管显示转换值-msp430 microcontroller' s AD converter, conversion value with digital display
ShowPicture
- 文件流形式显示图片，包括BMP,GIF,JGP,JEGP格式-File stream displayed images, including BMP, GIF, JGP, JEGP format
ucos2
- 一个基于bc3.1的uCOSII的经典实验源代码,通过测试。-Based on the uCOSII a classic experiment bc3.1 source code.
2052AD-car-vm
- STC 4 Voltage meter c program